In-memory computing : synthesis and optimization / Saeideh Shirinzadeh and Rolf Drechsler
نوع المادة : نصاللغة: الإنجليزية الناشر:Cham, Switzerland : Springer Nature, 2020تاريخ حقوق النشر: ©2020وصف:xi, 115 pages : illustrations ; 24 cmنوع المحتوى:- text
- unmediated
- volume
- 9783030180256
- 9783030180263
- 3030180263
- TK7895.M4 S5575 2020
نوع المادة | المكتبة الحالية | رقم الطلب | رقم النسخة | حالة | تاريخ الإستحقاق | الباركود | |
---|---|---|---|---|---|---|---|
كتاب | UAE Federation Library | مكتبة اتحاد الإمارات General Collection | المجموعات العامة | TK7895.M4 S5575 2020 (إستعراض الرف(يفتح أدناه)) | C.1 | Library Use Only | داخل المكتبة فقط | 30020000207116 | ||
كتاب | UAE Federation Library | مكتبة اتحاد الإمارات General Collection | المجموعات العامة | TK7895.M4 S5575 2020 (إستعراض الرف(يفتح أدناه)) | C.2 | المتاح | 30020000207115 |
Includes bibliographical references and index
Chapter 1: Introduction -- Chapter 2: Background -- Chapter 3: BDD Optimization and Approximation: A Multi-Criteria Approach -- Chapter 4: Synthesis for Logic-in-Memory Computing using RRAM -- Chapter 5: Compilation and Wear Le0veling for Programmable Logic-in-Memory (PLiM) Architecture -- Chapter 6: Conclusions
This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime. Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing;Describes automated compilation of programmable logic-in-memory computer architectures;Includes several effective optimization algorithm also applicable to classical logic synthesis;Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it