Digital design and Verilog HDL fundamentals / Joseph Cavanagh.

Includes index.

Number systems, number representations, and codes -- Number systems -- Binary number system -- Octal number system -- Decimal number system -- Hexadecimal number system -- Arithmetic operations -- Conversion between radices -- Number representations -- Sign magnitude -- Diminished-radix complement -- Radix complement -- Arithmetic operations -- Binary codes -- Binary weighted and nonweighted codes -- Binary-to-BCD conversion -- binary coded decimal-to-binary conversion -- Gray code -- Error detection and correction codes -- Parity -- Hamming code -- Cyclic redundancy check code -- Checksum -- Two-out-of-five code -- Horizontal and vertical parity check -- Serial data transmission -- Problems -- Minimization of switching functions -- Boolean algebra -- Algebraic minimization -- Karnaugh maps -- Map-entered variables -- Quine-McCluskey algorithm -- Petrick algorithm -- Problems -- Combinational logic -- Logic primitive gates -- Wired-and and Wired-or operations -- Three-state logic -- Functionally complete gates -- Logic macro functions -- Multiplexers -- Decoders -- Encoders -- Comparators -- Analysis of combinational logic -- Synthesis of combinational logic -- Problems.

Combinational logic design using verilog HDL -- Built-in primitives -- User-defined primitives -- Defining a user-defined primitive -- Combinational user-defined primitives -- Dataflow modeling -- Continuous assignment -- Reduction operators -- Conditional operator -- Relational operators -- Logical operators -- Bitwise operators -- Shift operators -- Behavioral modeling -- Initial statement -- Always statement -- Intrastatement delay -- Interstatement delay -- Blocking assignments -- Nonblocking assignments -- Conditional statement -- Case statement -- Loop statements -- Tasks -- Functions -- Structural modeling -- Module instantiation -- Ports -- Design examples 383 4.6 Problems -- Computer arithmetic -- Fixed-point addition -- Ripple-carry addition -- Carry lookahead addition -- Fixed-point subtraction -- Fixed-point multiplication -- Sequential add-shift -- Booth algorithm -- Bit-pair recoding -- Array multiplier -- Fixed-point division -- Restoring division -- Nonrestoring division -- Decimal addition -- Addition with sum correction -- Addition using multiplexers for sum correction -- Decimal subtraction -- Decimal multiplication -- Multiplication using read-only memory -- Decimal division -- Division using table lookup -- Floating-point arithmetic -- Floating-point addition/subtraction -- Floating-point multiplication -- Floating-point division -- Rounding methods -- Problems -- Computer arithmetic design using verilog HDL -- Fixed-point addition -- High-speed full adder -- Four-bit ripple adder -- Carry lookahead adder -- Fixed-point subtraction -- Fixed-point multiplication -- Booth algorithm -- Array multiplier -- Decimal addition -- binary coded decimal addition with sum correction -- binary coded decimal addition using multiplexers for sum correction -- Decimal subtraction -- Problems.

Sequential logic -- Analysis of synchronous sequential machines -- Machine alphabets -- Storage elements -- Classes of sequential machines -- Methods of analysis -- Analysis examples -- Synthesis of synchronous sequential machines -- Synthesis procedure -- Synchronous registers -- Synchronous counters -- Moore machines -- Mealy machines -- Output glitches -- Analysis of asynchronous sequential machines -- Fundamental-mode model -- Methods of analysis -- Hazards -- Oscillations -- Races -- Synthesis of asynchronous sequential machines -- Synthesis procedure -- Synthesis examples -- Analysis of pulse-mode asynchronous sequential machines -- Analysis procedure -- Synthesis of pulse-mode ssynchronous sequential machines -- Synthesis procedure -- Problems -- Sequential logic design using verilog HDL -- Synchronous sequential machines -- Asynchronous sequential machines -- Pulse-mode ssynchronous sequential machines -- Problems -- Programmable logic devices -- Programmable read-only memory -- Combinational logic -- Sequential logic -- Programmable array logic -- Combinational logic -- Sequential logic -- Programmable logic arrays -- Combinational logic -- Sequential logic -- Field-programmable gate arrays -- Problems.

Digital and analog conversion -- Operational amplifier -- Digital-to-analog conversion -- Binary-weighted resistor network digital-to-analog converter -- R-2R resistor network digital-to-analog converter -- Analog-to-digital conversion -- Comparators -- Counter analog-to-digital converter -- Successive approximation analog-to-tigital converter -- Simultaneous analog-to digital converter -- Problems -- Magnetic recording fundamentals -- Return to zero -- Nonreturn to zero -- Nonreturn to zero inverted -- Frequency modulation -- Phase encoding -- Modified frequency modulation -- Run-length limited -- Group-coded recording -- Peak shift -- Write precompensation -- Vertical recording -- Problems -- Additional topics in digital design -- Functional decomposition -- Iterative networks -- Hamming code -- Cyclic redundancy check code -- Residue checking -- Parity prediction -- Condition codes for addition -- Arithmetic and logic unit -- Memory -- Problems -- Appendix A: event queue -- Event handling for dataflow assignments -- Event handling for blocking assignments -- Event handling for nonblocking assignments -- Event handling for mixed blocking and nonblocking assignments -- Appendix B: verilog project procedure -- Appendix C: answers to select problems.