Integrated interconnect technologies for 3D nanoelectronic systems / Muhannad S. Bakir, James D. Meindl, editors.

Includes bibliographical references and index.

Today's microchips have nearly reached their performance limits. Various heat removal, power delivery, chip reliability, and input/output (I/O) signaling problems stand in the way of next-generation 3D gigascale, system-on-a-chip technology, and this cutting-edge guide describes the latest breakthroughs in microfluidics, high-density compliant electrical interconnects, and nanophotonics that are converging to solve them. Engineers get full details on state-of-the-art I/O interconnects and packaging, along with the latest advances and applications in power delivery design, analysis, and modeling. The book explores interconnect structures, materials, and packages for achieving high-bandwidth off-chip electrical communication. It brings readers up to speed with the latest heat removal technologies including chip-scale microchannel cooling, integrated micropumps and fluidic channels, and carbon nanotube interconnects.

Revolutionary silicon auxiliary technologies for the next era of gigascale integration -- Chip-package interaction and reliability impact on Cu/low-k interconnects -- Mechanically compliant I/O interconnects and packaging -- Power delivery to silicon -- On-ship supply noise modeling for gigascale 2D and 3D systems -- Off-chip signaling -- Optical interconnects for chip-to-chip signaling -- Monolithic optical interconnects -- Limits of current heat removal technologies and opportunities -- Active microfluidic cooling of integrated circuits -- Single and 3D chip cooling using microchannels and microfluidic chip I/O interconnects -- Carbon nanotube electrical and thermal properties and applications for interconnects -- 3D integration and packaging for memory -- 3D stacked die and silicon packaging with through-silicon vias, thinned silicon, and silicon-silicon interconnection technology -- Capacitive and inductive-soupling I/Os for 3D chips -- Wafer-level testing of gigascale integrated circuits.